The present invention relates to the field of programmable logic integrated circuits. More specifically, the present invention provides an enhanced programmable logic architecture, improving upon the composition, configuration, and arrangements of logic array blocks (LABs) and logic elements (LEs) and also the interconnections between these logic array blocks and logic elements.
Programmable Logic Devices (PLDs) are well known to those in the electronic art. Such programmable logic devices are commonly referred as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), PLDs (Programmable Logic Devices), EPLDs (Erasable Programmable Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known Classic(trademark), MAX(copyright) 5000, MAX(copyright) 7000, FLEX(copyright) 8000, and FLEX(copyright) 10K products made by Altera Corp.
PLDs are generally known in which many LABs are provided in a two-dimensional array. Further, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the LABs. LABs contain a number of individual programmable logic elements (LEs) which provide relatively elementary logic functions such as NAND, NOR, and exclusive OR.
Resulting from the continued scaling and shrinking of semiconductor device geometries which are used to form integrated circuits (also known as xe2x80x9cchipsxe2x80x9d), integrated circuits have progressively become smaller and denser. For programmable logic, it becomes possible to put greater numbers of programmable logic elements onto one integrated circuit. Furthermore, as the number of elements increases, it becomes increasingly important to improve the techniques and architectures used for interconnecting the elements and routing signals between the logic blocks.
While such devices have met with substantial success, such devices also meet with certain limitations, especially in situations in which the provision of more complex logic modules and additional or alternative types of interconnections between the logic modules would have benefits sufficient to justify the additional circuitry and programming complexity. There is also a continuing demand for logic devices with larger capacity. This produces a need to implement logic functions more efficiently and to make better use of the portion of the device which is devoted to interconnecting individual logic modules.
Furthermore, general purpose programmable logic devices are not generally especially designed for special applications such as emulation and ASIC prototyping. While these general purpose programmable logic devices may have served adequately in the initial development of these applications, it has become increasingly clear that for these applications, general purpose devices have some significant drawbacks. Many general purpose programmable logic devices typically emphasize speed and density above other goals. In order to be cost effective for most applications, a general purpose programmable logic architecture attempts to provide routing resources sufficient to give a good chance of fitting a design, and allowing the utilization of most of the available logic gates in the integrated circuit. However, with a general purpose programmable logic architecture, there is always a possibility that a given design or partition may not be implementable even through the gate count is within the rated capacity of the chip.
General purpose programmable logic devices have also typically not supported easy user-probing of internal state information inside the integrated circuit. In a general purpose PLD, any net which is of interest must be brought out to a pin explicitly in the design netlist. This augmentation of the netlist to provide for state observability and controllability often forces a significantly different set of placement decisions on the fitting and routing software. In these cases, the act of setting up to observe a signal may significantly alter the detailed timing of that or other signals. In short, an attempt to observe the event alters the event.
In an application such as an emulation system, there may be very many (e.g., possibly tens of thousands) programmable logic chips. A large design netlist will be partitioned over the collection of chips. If any (one or more) particular design partition does not fit into the assigned programmable logic chip, then the whole system will not be properly implemented. Consequently, it is vital that each and every partition fit and route individually. It is also important that incremental changes to the netlist should result in proportional impacts on the partitioning, fitting and routing. Furthermore, when used for emulation, the programmable logic device should have highly predictable routability, capacity, and timing characteristics.
Furthermore, when partitioning large designs into a number of programmable logic chips, it is desirable that the timing of the original netlist be preserved, which may not be the case if the programmable logic architecture does not provide features to allow this. When partitioning designs into a number of chips, signal path delays may be expanded, but not necessarily uniformly. These differences in signal path delays may introduce timing problems including skews, setup, and hold time violations which are not inherent in the design netlist. Furthermore, timing problems which are present in the design netlist will be hidden by the mapping into multiple programmable logic devices. Existing programmable logic architectures generally do not include adequate means for detecting these types of introduced timing problems and effective means for removing these problems.
As can be seen, an improved programmable logic device architecture is needed, especially programmable logic elements and interconnect networks which improve the organization of logic modules for particular applications including emulation and prototyping.
The present invention is a programmable logic device architecture. The architecture provides flexibility and a great deal of design routability. Many features of the architecture of the present invention ares especially well-suited for use in emulation and rapid prototyping applications.
This programmable logic architecture includes a logic block L2 and a diagnostic block interface. Logic block L2 includes a plurality of logic blocks L1 and an X2 programmable interconnect network. The X2 programmable interconnect network programmably couples signals between the plurality of logic blocks L1. Also, the X2 programmable interconnect network programmably couples signals between the logic block L2 and the diagnostic block interface and a plurality of programmable I/O pins of the integrated circuit. Each of the plurality of logic blocks L1 includes a plurality of logic blocks L0 and an X1 programmable interconnect. The X1 programmable interconnect network is used to programmably couple the logic blocks L0, and to programmably couple logic blocks L0 to the X2 programmable interconnect block. Each of the logic blocks L0 includes a plurality of LE logic elements and an X0 programmable interconnect network. In some embodiments of the present invention, logic blocks L0 may further include a secondary or auxiliary logic block. The X0 programmable interconnect network programmably couples signals between LEs, and the X1 interconnect network.
Using the architecture of the present invention, signals from the various logic blocks may be programmably coupled to other logic blocks, and to logic blocks at different levels. The architecture may also include a diagnostic block interface, which interfaces with logic block L2, for performing functions such as JTAG, functions, configuring logic block L2, initializing logic block L2, interfacing with off-chip diagnostic and test devices and equipment, and other similar functions. Logic block L2 interfaces with the other components of the integrated circuit such as the diagnostic block interface using the X2 programmable interconnect network.
In the present invention, the internal circuitry of the various logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications. For example, the present architecture provides, among other features: predictable logic, routing, and pin-out capacity; predictable and easily modified timing characteristics; and user-available diagnostic capabilities, including state observability. The present architecture may be used for debugging intensive applications where the probability of placement and routing success per chip is more of a concern than the operating speed path of the completed system.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying, drawings, in which like reference designations represent like features throughout the figures.